Fujitsu F2MC-8FX Instrukcja Użytkownika

FUJITSU SEMICONDUCTORCONTROLLER MANUALF2MC-8FX8-BIT MICROCONTROLLERPROGRAMMING MANUALCM26-00301-2E

vi

88CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.21 CLRI (CLeaR Interrupt flag)Set the I-flag to 0. CLRI (CLeaR Interrupt flag)Operation(I) ←

89CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSNByte Byte A TIXSPPCEPPSByte Byte01110001H I IL1 IL0 Z V CN00110001H I IL1 IL0 Z V

90CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.22 CMP (CoMPare Byte Data of Accumulator and Temporary Accumulator)Compare the byte data of AL

91CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 75XX 48XX 75XX 48Byte Byte(Before execution) (Aft

92CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.23 CMP (CoMPare Byte Data of Accumulator and Memory)Compare the byte data of AL with that of t

93CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 23 XX 2356 0180H56 0180H02 02Byte Byte(Before e

94CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.24 CMP (CoMPare Byte Data of Immediate Data and Memory) Compare the byte data of EA memory (me

95CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte01 2054 0120H54 0120H01 20Byte Byte(Before executi

96CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.25 CMPW (CoMPare Word Data of Accumulator and Temporary Accumulator)Compare the word data of A

97CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte86 7524 4886 7524 48Byte Byte(Before execution) (A

viiMain changes in this editionThe vertical lines marked in the left side of the page show the changes.Page Changes (For details, refer to main body.)

98CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.26 DAA (Decimal Adjust for Addition)When adding the correction value to AL by the state in the

99CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSTable 6.26-1 Decimal Adjustment Table (DAA)C-flag AL(bit7 to bit4)H-flag AL(bit3 to bit0)Correc

100CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.27 DAS (Decimal Adjust for Subtraction)Subtract the correction value from AL according to the

101CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS A TIXSPPCEPPSXX 2FXX 29NByte Byte10110000H I IL1 IL0 Z V CByte ByteN10110000H I

102CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.28 DEC (DECrement Byte Data of General-purpose Register)Decrement byte data of Ri by one. DE

103CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFE0112H0110H10R2R1R0FD0112H0110HR2R1R010Byte Byte

104CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.29 DECW (DECrement Word Data of Accumulator)Decrement word data of A by one. DECW (DECrement

105CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS78 22Byte Byte A TIXSPPCEPPS78 21Byte ByteByte Byte(Before execution) (After exec

106CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.30 DECW (DECrement Word Data of Extra Pointer)Decrement word data of EP by one. DECW (DECrem

107CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS12 34Byte Byte A TIXSPPCEPPS12 33Byte ByteByte Byte(Before execution) (After exec

viii

108CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.31 DECW (DECrement Word Data of Index Pointer)Decrement word data of IX by one. DECW (DECrem

109CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS16 27Byte Byte A TIXSPPCEPPS16 26Byte ByteByte Byte(Before execution) (After exec

110CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.32 DECW (DECrement Word Data of Stack Pointer)Decrement word data of SP by one. DECW (DECrem

111CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSByte Byte(Before execution) (After execution)Memory FFFFH Memory FFFFH0000H 0000HNZVC0000NZVC00

112CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.33 DIVU (DIVide Unsigned)Divide the word data of T by that of AL as an unsigned binary value.

113CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS00 OAByte Byte A TIXSPPCEPPS00 20Byte Byte01 41 00 01Byte Byte(Before execution)

114CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.34 INC (INCrement Byte Data of General-purpose Register)Add 1 to byte data of Ri. INC (INCre

115CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte56 0109H57 0109H0808R1R0R1R00108H 0108HByte Byte(

116CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.35 INCW (INCrement Word Data of Accumulator)Add 1 to word data of A. INCW (INCrement Word D

117CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte12 33 12 34Byte Byte(Before execution) (After exe

1CHAPTER 1OUTLINE ANDCONFIGURATION EXAMPLEOF F2MC-8FX CPUThis chapter outlines the F2MC-8FX CPU and explains its configuration by example.1.1 Outline

118CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.36 INCW (INCrement Word Data of Extra Pointer)Add 1 to word data of EP. INCW (INCrement Word

119CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte25 42 25 43Byte Byte(Before execution) (After exe

120CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.37 INCW (INCrement Word Data of Index Register)Add 1 to word data of IX. INCW (INCrement Wor

121CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte25 72 25 73Byte Byte(Before execution) (After exe

122CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.38 INCW (INCrement Word Data of Stack Pointer)Add 1 to word data of SP. INCW (INCrement Word

123CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFF FF 00 00Byte Byte(Before execution) (After exe

124CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.39 JMP (JuMP to address pointed by Accumulator)Transfer word data from A to PC. JMP (JuMP to

125CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX F0 89F0 89 F0 89Byte Byte(Before execution)

126CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.40 JMP (JuMP to effective Address)Branch to the PC value indicated by ext. JMP (JuMP to effe

127CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteE6D8 00 E6 54D800H2154E6D800H2154E654HByte Byte(B

2CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU1.1 Outline of F2MC-8FX CPUThe F2MC-8FX CPU is a high-performance 8-bit CPU designed for

128CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.41 MOV (MOVE Byte Data from Temporary Accumulator to Address Pointed by Accumulator)Transfer

129CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte01 20 01 200120HXX 0120H3FXX 3F XX 3FByte Byte(Befo

130CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.42 MOV (MOVE Byte Data from Memory to Accumulator)Transfer byte data from EA memory (memory e

131CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte11 22 11 510383H51 0383H51XX XX XX 22 06 06Byte B

132CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.43 MOV (MOVE Immediate Byte Data to Memory)Transfer byte immediate data to EA memory (memory

133CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0202HXX0202H3502 00 02 00 0200H0200H(IX+2)(IX+2)B

134CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.44 MOV (MOVE Byte Data from Accumulator to memory)Transfer bytes (data from AL) immediate dat

135CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 06XX 06 XX 06 0202H0202H03 03Byte Byte(Before

136CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.45 MOVW (MOVE Word Data from Temporary Accumulator to Address Pointed by Accumulator)Transfer

137CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX01 780178H0178H0179H0179HFB AA01 78FB AAXXFBAAB

3CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU1.2 Configuration Example of Device Using F2MC-8FX CPUThe CPU, ROM, RAM and various resou

138CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.46 MOVW (MOVE Word Data from Memory to Accumulator)Transfer word data from EA and EA + 1 memo

139CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteEF01 020150H0150HXX XXEF 2301 0223EF23(IX+1)0151H

140CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.47 MOVW (MOVE Word Data from Extra Pointer to Accumulator)Transfer word data from EP to A. M

141CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX96 3296 32 96 32Byte Byte(Before execution)

142CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.48 MOVW (MOVE Word Data from Index Register to Accumulator)Transfer word data from IX to A.

143CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX87 2387 23 87 23Byte Byte(Before execution)

144CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.49 MOVW (MOVE Word Data from Program Status Register to Accumulator)Transfer word data from P

145CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX78 1878 18 78 18Byte Byte(Before execution)

146CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.50 MOVW (MOVE Word Data from Program Counter to Accumulator)Transfer word data from PC to A.

147CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XXF0 62 F0 62F0 62Byte Byte(Before execution)

4CHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU

148CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.51 MOVW (MOVE Word Data from Stack Pointer to Accumulator)Transfer word data from SP to A.

149CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX69 05 69 0569 05Byte Byte(Before execution)

150CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.52 MOVW (MOVE Word Data from Accumulator to Memory)Transfer word data from A to EA and EA + 1

151CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte10 56 10 56XXXX0094H0093H56100094H0093H00 00Byte

152CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.53 MOVW (MOVE Word Data from Accumulator to Extra Pointer)Transfer word data from A to EP. M

153CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte87 65 87 65XX XX 87 65Byte Byte(Before execution)

154CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.54 MOVW (MOVE Immediate Word Data to Extra Pointer)Transfer word immediate data to EP. MOVW

155CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX 23 45Byte Byte(Before execution) (After exe

156CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.55 MOVW (MOVE Word Data from Accumulator to Index Register)Transfer word data from A to IX.

157CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX56 4356 4356 43Byte Byte(Before execution) (

5CHAPTER 2MEMORY SPACEThis chapter explains the F2MC-8FX CPU memory space.2.1 CPU Memory Space2.2 Memory Space and Addressing

158CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.56 MOVW (MOVE Immediate Word Data to Index Register)Transfer word immediate data to IX. MOVW

159CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX XX 45 67Byte Byte(Before execution) (After exe

160CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.57 MOVW (MOVE Word data from Accumulator to Program Status Register)Transfer word data from A

161CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSXXXXNZVCByte ByteMemory FFFFHByte 0000H(Before execution) A TIXSPPCEP

162CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.58 MOVW (MOVE Immediate Word Data to Stack Pointer)Transfer word immediate data to SP. MOVW

163CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 67 89Byte Byte(Before execution) (After executio

164CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.59 MOVW (MOVE Word data from Accumulator to Stack Pointer)Transfer word data from A to SP. M

165CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX43 2143 21 43 21Byte Byte(Before execution) (Afte

166CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.60 MULU (MULtiply Unsigned)Multiply the byte data of AL and TL as unsigned binary values. Ret

167CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 40 XX 40XX 20 08 00Byte Byte(Before execution)

6CHAPTER 2 MEMORY SPACE2.1 CPU Memory Space All of the data, program, and I/O areas managed by the F2MC-8FX CPU are assigned to the 64 Kbyte memory s

168CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.61 NOP (NoOPeration)No operation NOP (NoOPeration)Operation————Assembler formatNOPCondition

169CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte BytePC+1PCPC+1PCByte Byte(Before execution) (After ex

170CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.62 OR (OR Byte Data of Accumulator and Temporary Accumulator to Accumulator)Carry out the log

171CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX 41 XX 4115 23 15 63Byte Byte(Before execution)

172CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.63 OR (OR Byte Data of Accumulator and Memory to Accumulator)Carry out the logical OR on AL a

173CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte15 3215 7656 0122H01 2256 0122H01 22Byte Byte(Befor

174CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.64 ORW (OR Word Data of Accumulator and Temporary Accumulator to Accumulator)Carry out the lo

175CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte57 2377 6333 41 33 41Byte Byte(Before execution)

176CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.65 PUSHW (PUSH Word Data of Inherent Register to Stack Memory)Subtract 2 from the value of SP

177CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0222H02 2012 3402 22XX0222H341212 340220HByte Byt

7CHAPTER 2 MEMORY SPACE2.2 Memory Space and AddressingIn addressing by the F2MC-8FX CPU, the applicable addressing mode related to memory access may

178CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.66 POPW (POP Word Data of Intherent Register from Stack Memory)Transfer the word value from t

179CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0233H02 35XX XX02 3326310235H263131 260233HByte Byt

180CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.67 RET (RETurn from subroutine)Return the contents of PC saved in the stack. When this instru

181CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0206H02 08F8 0902 0610FC0208H10FCFC 100206HByte B

182CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.68 RETI (RETurn from Interrupt)Return the contents of PS and PC saved in the stack. Return PS

183CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0206H02 OAXX02 0610FC84080208HFC 100206H10FC8408XX

184CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.69 ROLC (Rotate Byte Data of Accumulator with Carry to Left)Shift byte data of AL with a carr

185CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX ABXX 55Byte Byte(Before execution) (After execut

186CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.70 RORC (Rotate Byte Data of Accumulator with Carry to Right)Shift byte data of AL with a car

187CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteXX AAXX 55Byte Byte(Before execution) (After exec

8CHAPTER 2 MEMORY SPACEFigure 2.2-1 Memory Space and Addressing: Direct addressing: Extended addressing: Bit direct addressing: Index addressing: Po

188CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.71 SUBC (SUBtract Byte Data of Accumulator from Temporary Accumulator with Carry to Accumulat

189CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte12 1112 2376 34 76 34Byte Byte(Before execution)

190CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.72 SUBC (SUBtract Byte Data of Memory from Accumulator with Carry to Accumulator)Subtract the

191CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte12 FD12 34Byte Byte(Before execution) (After exec

192CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.73 SUBCW (SUBtract Word Data of Accumulator from Temporary Accumulator with Carry to Accumula

193CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSATIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte24 2032 1456 34 56 34Byte Byte(Before execution) (A

194CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.74 SETB (Set Direct Memory Bit)Set the contents of 1 bit (indicated by 3 lower bits (b) of mn

195CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte ByteFFFFH0000H A TIXSPPCEPPSByte ByteFFFFH0000H00X0 0000 0032H 0032H0010 000

196CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.75 SETC (SET Carry flag)Set the C-flag to 1. SETC (SET Carry flag)Operation(C) ← 1Assembler

197CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFFFFH0000HFFFFH0000HByteByte(Before execution) (A

9CHAPTER 2 MEMORY SPACE2.2.1 Data AreaThe F2MC-8FX CPU data area can be divided into the following three for each purpose:• General-purpose register

198CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.76 SETI (SET Interrupt flag)Set the I-flag to 1 (enable an interrupt). SETI (SET Interrupt f

199CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS A TIXSPPCEPPSNByte ByteH I IL1 IL0 Z V CByte ByteNH I IL1 IL0 Z V CFFFFH0000HFFF

200CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.77 SWAP (SWAP Byte Data Accumulator "H" and Accumulator "L")Exchange the

201CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA AA 32FFFFH0000HFFFFH0000HByteByte(Before ex

202CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.78 XCH (eXCHange Byte Data Accumulator "L" and Temporary Accumulator "L")

203CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA 32 7955 79 55 AAFFFFH0000HFFFFH0000HByteByt

204CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.79 XCHW (eXCHange Word Data Accumulator and Extrapointer)Exchange the word data of A for that

205CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA 55 7955 79 32 AAFFFFH0000HFFFFH0000HByteByt

206CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.80 XCHW (eXCHange Word Data Accumulator and Index Register)Exchange the word data of A for th

207CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA 55 7955 79 32 AAFFFFH0000HFFFFH0000HByteByt

10CHAPTER 2 MEMORY SPACEFigure 2.2-3 Example of Saving Data in Stack AreaFigure 2.2-4 Example of Returning Data from Stack Area Direct AreaThe dir

208CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.81 XCHW (eXCHange Word Data Accumulator and Program Counter)Exchange the word data of PC for

209CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteF0 C7 F1 7AF1 79 F0 C7FFFFH0000HFFFFH0000HByteByt

210CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.82 XCHW (eXCHange Word Data Accumulator and Stack Pointer)Exchange the word data of A for tha

211CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA 55 7955 79 32 AAFFFFH0000HFFFFH0000HByteByt

212CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.83 XCHW (eXCHange Word Data Accumulator and Temporary Accumulator)Exchange the word data of A

213CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte32 AA 55 7955 79 32 AAFFFFH0000HFFFFH0000HByteByt

214CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.84 XOR (eXclusive OR Byte Data of Accumulator and Temporary Accumulator to Accumulator)Carry

215CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSFFFFH0000HFFFFH0000HByteByte(Before execution) (After execution)Memory MemoryNZVC0000NZVC0000 A

216CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.85 XOR (eXclusive OR Byte Data of Accumulator and Memory to Accumulator)Carry out the logical

217CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte54 32 54 2001 22 01 2212 0122H 12 0122HFFFFH0000H

11CHAPTER 2 MEMORY SPACE2.2.2 Program AreaThe program area in the F2MC-8FX CPU includes the following two:• Vector call instruction table• Reset and

218CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.86 XORW (eXclusive OR Word Data of Accumulator and Temporary Accumulator to Accmulator)Carry

219CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte57 23 64 6233 41 33 41FFFFH0000HFFFFH0000HByteByt

220CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS

221APPENDIXThe appendix contains instruction and bus operation lists and an instruction map.APPENDIX A Instruction ListAPPENDIX B Bus Operation List

222APPENDIX APPENDIX A Instruction ListAppendix A contains lists of instructions used in the assembler.A.1 F2MC-8FX CPU Instruction OverviewA.2 Ope

223APPENDIX A Instruction ListA.1 F2MC-8FX CPU Instruction OverviewThis section explains the F2MC-8FX CPU instructions. F2MC-8FX CPU Instruction Ove

224APPENDIX Sign of the Instruction ListTable A.1-1 explains the sign used by describing the instruction code in the table.Table A.1-1 Sign of the

225APPENDIX A Instruction List Item in Instruction TableTable A.1-2 explains the item of instruction table. Table A.1-2 Item in Instruction TableIt

226APPENDIX A.2 Operation ListTable A.2-1 is the operation list for transfer instructions. Table A.2-2 is the operation list for operation instructio

227APPENDIX A Instruction List19 MOVW ext, A 5 3 (ext) ← (AH), (ext+1) ← (AL)– – – – – – – D420 MOVW @EP, A 3 1 ((EP)) ← (AH), ((EP)+1) ← (AL)– – – –

12CHAPTER 2 MEMORY SPACEFFFCH: ReservedFFFDH: ModeNote: The actual number varies according to the product.Use the interrupt number #22 and #23 exclus

228APPENDIX Notes:1. In byte transfer to A, T ← A is only low bytes.2. The operands of an instruction with two or more operands should be stored in t

229APPENDIX A Instruction List15 IINC Ri 3 1 (Ri) ← (Ri)+1 – – – + + + – C8 to CF16 INCW EP 1 1 (EP) ← (EP)+1 – – – – – – – C317 INCW IX 1 1

230APPENDIX 38 DAS 1 1 decimal adjust for subtraction– – – + + + + 9439 XOR A 1 1 (A) ← (AL) ∀ (TL) – – – + + R – 5240 XOR A, #d8 2 2 (A) ← (AL) ∀ d8

231APPENDIX A Instruction ListTable A.2-3 Operation List (for Branch Instructions)No MNEMONIC ~ # OPERATION TL TH AH NZVC OP CODE1BZ/BEQ rel (diver

232APPENDIX Table A.2-4 Operation List (for Other Instructions)No MNEMONIC ~ # OPERATION TL TH AH N Z V C OP CODE1 PUSHW A 4 1 (SP) ← (SP)-2, ((SP))

233APPENDIX A Instruction ListA.3 Flag Change TableTable A.3-1 is the flag change table for transfer instructions. Table A.3-2 is the flag change tab

234APPENDIX MOVW A, EP N: Not changedMOVW EP, #d16 Z: Not changedMOVW IX, A V: Not changedMOVW A, IX C: Not changedMOVW SP, AMOVW A, SPMOVW SP, #d16M

235APPENDIX A Instruction ListTable A.3-2 Flag Change Table (for Operation Instructions) (1/3)Instruction Flag changeADDC A, Ri N: Set to 1 if the r

236APPENDIX DECW EP N: Not changedDECW IX Z: Not changedDECW SP V: Not changedC: Not changedDECW A N: Set to 1 if the result of operation is negative

237APPENDIX A Instruction ListXORW A N: Set to 1 if the result of operation is negative and set to 0 in other cases.Z: Set to 1 if the result of oper

13CHAPTER 2 MEMORY SPACE2.2.3 Arrangement of 16-bit Data in Memory SpaceThe F2MC-8FX CPU can perform 16-bit data transfer and arithmetic operation th

238APPENDIX Table A.3-3 Flag Change Table (for Branch Instructions)Instruction Flag changeBZ rel/BEQ rel N: Not changedBNZ rel/BNE rel Z: Not change

239APPENDIX A Instruction ListTable A.3-4 Flag Change Table (for Other Instructions)Instruction Flag changePUSHW A N: Not changedPUSHW IX Z: Not cha

240APPENDIX APPENDIX B Bus Operation ListTable B-1 is a bus operation list. Bus Operation ListTable B-1 Bus Operation List (1/11)CODE MNEMONIC ~ Cy

241APPENDIX B Bus Operation List05 MOV A, dir 3 1 N +2 The following instruction10 015 CMP A, dir 2 dir address Data 1 0 025 ADDC A, dir 3 N +3

242APPENDIX 08 - 0F MOV A, Ri 2 1 N +2 The following following instruction10 018 - 1F CMP A, Ri 2 Rn address Data 1 0 028 - 2F ADDC A, Ri38 - 3F

243APPENDIX B Bus Operation ListF4 XCHW A, PC 3 1 N +2 Data of N +2 1 0 02 Address divergence The following instruction10 03 Address divergence +1Th

244APPENDIX C4 MOVW A, ext 5 1 N +2 ext (L byte) 1 0 02 N +3 The following instruction10 03 ext address Data (H byte) 1 0 04 ext+1 address Data (L by

245APPENDIX B Bus Operation ListC7 MOVW A, @EP 3 1 N +2 The following following instruction10 02 (EP) address Data(H byte) 1 0 03 (EP)+1 address Data

246APPENDIX 87 MOV @EP, #d8 3 1 N +2 The followinginstruction10 02 (EP) address Data 0 1 03 N +3 The following following instruction10 097 CMP @EP, #

247APPENDIX B Bus Operation List93 MOVW A, @A 3 1 N +2 The following following instruction10 02 (A) address Data (H byte) 1 0 03 (A) +1 address Data

14CHAPTER 2 MEMORY SPACE

248APPENDIX F8 BNC rel DivergenceF9 BC rel 4 1 N +2 Data of N +2 1 0 0FA BP rel 2 N +3 Data of N +3 1 0 0FB BN rel 3 Address divergence aheadThe foll

249APPENDIX B Bus Operation List31 CALL ext 6 1 N +2 Address divergence ahead (L)10 02 −− 00 03 SP -1 Return address (L) 0 1 04 SP -2 Return address

250APPENDIX − INTERRUPT 9 1 N +2 Data of N +2 1 0 02 Vector address Vector (H) 1 0 03 Vector address +1 Vector (L) 1 0 04 SP -1 Return address (L) 0

251APPENDIX C Instruction MapAPPENDIX C Instruction MapTable C-1 is an instruction map. Instruction MapTable C-1 Instruction Map

252APPENDIX

253INDEXINDEXThe index follows on the next page.This is listed in alphabetic order.

254INDEXIndexSymbols#immImmediate Addressing (#imm) ...41#kVector Addressing (#k)...42@EP

255INDEXBHSBNC (Branch relative if C=0)/BHS (Branch if Higheror Same) ...74Bit Direct AddressingBit Direct

256INDEXextExtended Addressing (ext) ...40Extended AddressingExtended Addressing (ext) ...

257INDEXMOVW (MOVE Word Data from Program Counter toAccumulator)...146MOVW (MOVE Word Data from Program StatusRegis

15CHAPTER 3REGISTERSThis chapter explains the F2MC-8FX dedicated registers and general-purpose registers.3.1 F2MC-8FX Registers3.2 Program Counter (

258INDEXSWAPSWAP (SWAP Byte Data Accumulator ’H’and Accumulator ’L’) ...200TTDirect Data Transfer from Temporary Accumula

CM26-00301-2EFUJITSU SEMICONDUCTOR • CONTROLLER MANUALF2MC-8FX8-BIT MICROCONTROLLERPROGRAMMING MANUALFebruary 2008 the second editionPublished FUJITSU

16CHAPTER 3 REGISTERS3.1 F2MC-8FX RegistersIn the F2MC-8FX series, there are two types of registers: dedicated registers in the CPU, and general-purp

17CHAPTER 3 REGISTERS3.2 Program Counter (PC) and Stack Pointer (SP)The program counter (PC) and stack pointer (SP) are application-specific register

FUJITSU LIMITEDF2MC-8FX8-BIT MICROCONTROLLERPROGRAMMING MANUAL

18CHAPTER 3 REGISTERS3.3 Accumulator (A) and Temporary Accumulator (T)The accumulator (A) and temporary accumulator (T) are application-specific regi

19CHAPTER 3 REGISTERSFigure 3.3-3 Data Transfer between Accumulator (A) and Temporary Accumulator (T) (16-bit Transfer)Figure 3.3-4 Data Transfer b

20CHAPTER 3 REGISTERS3.3.1 How To Use The Temporary Accumulator (T)The F2MC-8FX CPU has a special-purpose register called a temporary accumulator. Th

21CHAPTER 3 REGISTERS3.3.2 Byte Data Transfer and Operation of Accumulator (A) and Temporary Accumulator (T) When data transfer to the accumulator (A

22CHAPTER 3 REGISTERS Direct Data Transfer from Temporary Accumulator (T)The temporary accumulator (T) is basically temporary storage for the accumu

23CHAPTER 3 REGISTERS3.4 Program Status (PS)The program status (PS) is a 16-bit application-specific register existing in the CPU.In upper byte of pr

24CHAPTER 3 REGISTERS Program Status (PS) FlagsThe program status flags are explained below.•H flagThis flag is 1 if a carry from bit 3 to bit 4 or

25CHAPTER 3 REGISTERSThis flag is 1 when a two’s complement overflow occurs and is 0 when one does not as the result of anoperation.•C flagThis flag

26CHAPTER 3 REGISTERS3.5 Index Register (IX) and Extra Pointer (EP)The index register (IX) and extra pointer (EP) are 16-bit application-specific reg

27CHAPTER 3 REGISTERS3.6 Register BanksThe register bank register is an 8-bit general-purpose register existing in memory. There are eight registers

28CHAPTER 3 REGISTERS3.7 Direct BanksThe direct bank is in 0080H to 047FH of direct area, and composed of 128 bytes × 8 banks. The access that uses d

29CHAPTER 4INTERRUPT PROCESSINGThis chapter explains the functions and operation of F2MC-8FX interrupt processing.4.1 Outline of Interrupt Operation4

30CHAPTER 4 INTERRUPT PROCESSING4.1 Outline of Interrupt OperationF2MC-8FX series interrupts have the following features:• Four interrupt priority le

31CHAPTER 4 INTERRUPT PROCESSINGFigure 4.1-1 shows the flow diagram of F2MC-8FX interrupt operation.Figure 4.1-1 Outline of F2MC-8FX Interrupt Opera

32CHAPTER 4 INTERRUPT PROCESSING4.2 Interrupt Enable/Disable and Interrupt Priority FunctionsIn the F2MC-8FX series, interrupt requests are transferr

33CHAPTER 4 INTERRUPT PROCESSINGFigure 4.2-1 Relationship between Interrupt Request and Interrupt Level in ResourcesInterrupt request F/FResource #1

34CHAPTER 4 INTERRUPT PROCESSING4.3 Creating an Interrupt Processing ProgramIn the F2MC-8FX series, basically, interrupt requests from resources are

35CHAPTER 4 INTERRUPT PROCESSINGFigure 4.3-2 Interrupt Response TimeCPU operationInterrupt handlingNormal instruction executionInterrupt processing

36CHAPTER 4 INTERRUPT PROCESSING4.4 Multiple InterruptThe F2MC-8FX CPU can have a maximum of four levels as maskable interrupts. These can be used to

37CHAPTER 4 INTERRUPT PROCESSING4.5 Reset OperationIn the F2MC-8FX series, when a reset occurs, the flag of program status is 0 and the IL bit is set

iPREFACE Purpose and AudienceThe F2MC-8FX is original 8-bit one-chip microcontrollers that support application specific IC(ASIC). It can be widely ap

38CHAPTER 4 INTERRUPT PROCESSING

39CHAPTER 5CPU SOFTWAREARCHITECTUREThis chapter explains the instructions for the F2MC-8FX CPU.5.1 Types of Addressing Modes5.2 Special Instructions

40CHAPTER 5 CPU SOFTWARE ARCHITECTURE5.1 Types of Addressing ModesThe F2MC-8FX CPU has the following ten addressing modes:• Direct addressing (dir)•

41CHAPTER 5 CPU SOFTWARE ARCHITECTURE Index Addressing (@IX+off)This addressing mode, indicated as "@IX+off" in the instruction list, is u

42CHAPTER 5 CPU SOFTWARE ARCHITECTURE Vector Addressing (#k)This addressing mode, indicated as "#k" in the instruction list, is used for b

43CHAPTER 5 CPU SOFTWARE ARCHITECTURE5.2 Special InstructionsIn the F2MC-8FX series, the following six special instructions are available:•JMP @A• MO

44CHAPTER 5 CPU SOFTWARE ARCHITECTURE MULU AThis instruction is used for multiplying 8 bits of the AL by 8 bits of the TL without a sign and stores

45CHAPTER 5 CPU SOFTWARE ARCHITECTUREFigure 5.2-1 Example of Using XCHW A, PC CALLV #kThis instruction is used for branching to a subroutine addres

46CHAPTER 5 CPU SOFTWARE ARCHITECTUREPC PCSP(-2)SPDCHDCHFEHFEH79H56H5678HBefore executionAfter execution [Example]CALLV #31234H1232HFEDCH1233H1232H12

47CHAPTER 6DETAILED RULESFOR EXECUTIONINSTRUCTIONSThis chapter explains each execution instruction, used in the assembler, in reference format.All exe

ii Copyright© 2004-2008 FUJITSU LIMITED All rights reserved.• The contents of this document are subject to change without notice. Customers are advis

48CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.1 ADDC (ADD Byte Data of Accumulator and Temporary Accumulator with Carry to Accumulator)Add t

49CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS12 3456 78Byte ByteByte A TIXSPPCEPPS12 AC56 78Byte ByteByte(Before execution) (Af

50CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.2 ADDC (ADD Byte Data of Accumulator and Memory with Carry to Accumulator)Add the byte data of

51CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS12 34Byte Byte A TIXSPPCEPPS12 5AByte ByteByte Byte(Before execution) (After execu

52CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.3 ADDCW (ADD Word Data of Accumulator and Temporary Accumulator with Carry to Accumulator)Add

53CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS12 3456 78Byte Byte A TIXSPPCEPPS68 AD56 78Byte ByteByte Byte(Before execution) (A

54CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.4 AND (AND Byte Data of Accumulator and Temporary Accumulator to Accumulator)Carry out the log

55CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS12 34XX 2CByte Byte A TIXSPPCEPPS12 24XX 2CByte ByteByte Byte(Before execution) (A

56CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.5 AND (AND Byte Data of Accumulator and Memory to Accumulator)Carry out the logical AND on the

57CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS02 53Byte Byte A TIXSPPCEPPS02 11Byte Byte31 0123H31 0123H01 23 01 23Byte Byte(Bef

iiiCONTENTSCHAPTER 1 OUTLINE AND CONFIGURATION EXAMPLE OF F2MC-8FX CPU ... 11.1 Outline of F2MC-8FX CPU ...

58CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.6 ANDW (AND Word Data of Accumulator and Temporary Accumulator to Accumulator)Carry out the lo

59CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPS56 6334 32Byte Byte A TIXSPPCEPPS14 2234 32Byte ByteByte Byte(Before execution) (A

60CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.7 BBC (Branch if Bit is Clear) Branch when the value of bit b in dir memory is 0. Branch addre

61CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteB0 E800HE8 00 E7 FEXXXX XXX0 0084Hbit0B0 E800HXXXX

62CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.8 BBS (Branch if Bit is Set)Branch when the value of bit b in dir memory is 1. Branch address

63CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteB0 E800HE8 00 E7 FEXXXX XXX10084Hbit0B0 E800HXXXX

64CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.9 BC (Branch relative if C=1)/BLO (Branch if LOwer)Execute the next instruction if the C-flag

65CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFEE8 02 E8 04F802HE802HF9FEF9E804HByte Byte(Before

66CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.10 BGE (Branch Great or Equal: relative if larger than or equal to Zero)Execute the next instr

67CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte02F4 56 F4 58F456H F456HFE02FEF458HByte Byte(Befor

iv 6.7 BBC (Branch if Bit is Clear) ...

68CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.11 BLT (Branch Less Than zero: relative if < Zero)Execute the next instruction if the logic

69CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte02F4 56 F4 5AF456H F456HFF02FFF45AHF458H F458HByte

70CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.12 BN (Branch relative if N = 1)Execute the next instruction if the N-flag is 0 and the branch

71CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFC 5F FC 63FC5FH FC5FH02FBFC63H02FBByte Byte(Befor

72CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.13 BNZ (Branch relative if Z = 0)/BNE (Branch if Not Equal)Execute the next instruction if the

73CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFAFE 1E FE 20FE1EH FE1EHFCFAFCFE20HByte Byte(Befor

74CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.14 BNC (Branch relative if C = 0)/BHS (Branch if Higher or Same)Execute the next instruction i

75CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte01E8 02 E8 05E802H E802HF801F8E805HE804HE804HByte

76CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.15 BP (Branch relative if N = 0: PLUS)Execute the next instruction if the N-flag is 1 and the

77CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte04FC 5F FC 61FC5FH FC5FHFA04FAFC61HByte Byte(Befor

v6.54 MOVW (MOVE Immediate Word Data to Extra Pointer) ... 1546.55 MOVW (MOVE Word Data

78CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.16 BZ (Branch relative if Z = 1)/BEQ (Branch if Equal)Execute the next instruction if the Z-fl

79CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteFDFE 1E FE 1AFE1EHFE1AHFAFDFE1EHFAFE20HByte Byte(B

80CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.17 CALL (CALL subroutine)Branch to address of ext. Return to the instruction next to this one

81CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteF6 23 FC 00020AH0208H020AH26F602 OA 02 08Byte Byte

82CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.18 CALLV (CALL Vectored subroutine)Branch to the vector address (VA) of vct. Return to the ins

83CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONSTable 6.18-1 Call Storage Address of Vector Call InstructionVector address (VA)InstructionLower

84CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.19 CLRB (Clear direct Memory Bit)Set the contents of 1 bit (indicated by 3 lower bits (b) of m

85CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte Byte0084H0000 000X0084H0000 000000 00Byte Byte(Before

86CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS6.20 CLRC (Clear Carry flag)Set the C-flag to 0. CLRC (Clear Carry flag)Operation(C) ← 0Assembl

87CHAPTER 6 DETAILED RULES FOR EXECUTION INSTRUCTIONS A TIXSPPCEPPSByte Byte A TIXSPPCEPPSByte ByteByte Byte(Before execution) (After execution)Memor