Fujitsu C141-E090-02EN Instrukcja Użytkownika

C141-E090-02ENMPE3xxxAHDISK DRIVESPRODUCT MANUAL

C141-E090-01EN ix5.2.1 I/O registers ...

C141-E090-01EN 5 - 35Table 5.6 Features register values and settable modesFeatures Register Drive operation modeX‘02’ Enables the write cache function

C141-E090-01EN5 - 36At command issuance (I/O registers setting contents)1F7H(CM) 1 1 1 0 1 1 1 11F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H

C141-E090-01EN 5 - 37(15) SET MULTIPLE MODE (X'C6')This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLEcommands.

C141-E090-01EN5 - 38Regarding software reset, the mode set prior to software reset is retained after software reset.The parameters for the multiple co

C141-E090-01EN 5 - 39Table 5.7 Diagnostic codeCode Result of diagnosticX‘01’X‘03’X‘05’X‘8x’No error detected.Data buffer compare errorROM sum check er

C141-E090-01EN5 - 40The READ LONG command supports only single sector operation.At command issuance (I/O registers setting contents)1F7H(CM) 0 0 1 0 0

C141-E090-01EN 5 - 41At command issuance (I/O registers setting contents)1F7H(CM) 0 0 1 1 0 0 1 R1F6H(DH)×L×DV Head No. /LBA [MSB]1F5H(CH)1F4H(CL)1F3H

C141-E090-01EN5 - 42At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H

C141-E090-01EN 5 - 43(22) IDLE (X'97' or X'E3')Upon receipt of this command, the device sets the BSY bit of the Status register, a

C141-E090-01EN5 - 44At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H

C141-E090-01ENx5.6.3.5 Device terminating an Ultra DMA data in burst... 5 - 925.6.3.6 Host

C141-E090-01EN 5 - 45(24) STANDBY (X'96' or X'E2')Upon receipt of this command, the device sets the BSY bit of the Status register

C141-E090-01EN5 - 46At command issuance (I/O registers setting contents)1F7H(CM) X'94' or X'E0'1F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1

C141-E090-01EN 5 - 47At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2

C141-E090-01EN5 - 48At command issuance (I/O registers setting contents)1F7H(CM) X'98' or X'E5'1F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1

C141-E090-01EN 5 - 49Table 5.8 Features Register values (subcommands) and functionsFeatures Resister FunctionX’D0’ SMART Read Attribute Values:A devi

C141-E090-01EN5 - 50Alternative, the device must issue the SMART Enable-Disable Attribute AutoSavesubcommand (FR register = D2h) to use a feature whic

C141-E090-01EN 5 - 51The attribute value information is 512-byte data; the format of this data is shown below. Thehost can access this data using the

C141-E090-01EN5 - 52Table 5.10 Format of insurance failure threshold value dataByte Item0001Data format version number02Attribute 1 Attribute ID03 In

C141-E090-01EN 5 - 53• Attribute IDThe attribute ID is defined as follows:Attribute ID Attribute name0 (Indicates unused attribute data.)1 Read error

C141-E090-01EN5 - 54• Raw attribute valueRaw attributes data is retained.• Failure prediction capability flagBit 0: The attribute value data is saved

C141-E090-01EN xiFIGURESpage1.1 Current fluctuation (Typ.) when power is turned on... 1 - 72.1 Dis

C141-E090-01EN 5 - 55(29) FLUSH CACHE (X ‘E7’)This command is use by the host to request the device to flush the write cache. If the writecache is to

C141-E090-01EN5 - 56(30) SECURITY DISABLE PASSWORD (F6h)This command invalidates the user password already set and releases the lock function.The host

C141-E090-01EN 5 - 57At command issuance (I-O registers setting contents)1F7H(CM) 1 1 1 1 0 1 1 01F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1

C141-E090-01EN5 - 58At command issuance (I-O registers setting contents)1F7H(CM) 1 1 1 1 0 0 1 11F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H

C141-E090-01EN 5 - 59At command issuance (I-O registers setting contents)1F7H(CM) 1 1 1 1 0 1 0 01F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1

C141-E090-01EN5 - 60• READ DMA • WRITE DMA • SECURITY DISABLE PASSWORD• READ LONG • WRITE LONG • SECURITY FREEZE LOCK• READ MULTIPLE • WRITE MULTIPLE

C141-E090-01EN 5 - 61Table 5.12 Contents of SECURITY SET PASSWORD dataWord Contents0 Control wordBit 0 Identifier0 = Sets a user password.1 = Sets a

C141-E090-01EN5 - 62At command issuance (I-O registers setting contents)1F7H(CM) 1 1 1 1 0 0 0 11F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1H

C141-E090-01EN 5 - 63At command issuance (I-O registers setting contents)1F7H(CM) 1 1 1 1 0 0 1 01F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1

C141-E090-01EN5 - 64At command issuance (I/O registers setting contents)1F7H(CM) 1 1 1 1 1 0 0 11F6H(DH)×L×DV Max head/LBA [MSB]1F5H(CH)1F4H(CL)1F3H(S

C141-E090-01ENxii5.4 WRITE SECTOR(S) command protocol... 5 - 705.5 Protocol for t

C141-E090-01EN 5 - 65At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)× × ×DV Max head/LBA [MSB]1F5H(CH)1F4

C141-E090-01EN5 - 665.3.3 Error postingTable 5.14 lists the defined errors that are valid for each command.Table 5.14 Command code and parametersComma

C141-E090-01EN 5 - 675.4 Command ProtocolThe host should confirm that the BSY bit of the Status register of the device is 0 prior to issuea command. I

C141-E090-01EN5 - 68Status readStatus read*1 When the IDD receives a command that hits the cache data during read-ahead, and transfers data from

C141-E090-01EN 5 - 69Note:For transfer of a sector of data, the host needs to read Status register (X'1F7') in order toclear INTRQ (interrup

C141-E090-01EN5 - 70a) The host writes any required parameters to the Features, Sector Count, Sector Number,Cylinder, and Device/Head registers.b) The

C141-E090-01EN 5 - 71Note:For transfer of a sector of data, the host needs to read Status register (X'1F7') in order toclear INTRQ (interrup

C141-E090-01EN5 - 725.4.4 Other commands• READ MULTIPLE• SLEEP• WRITE MULTIPLESee the description of each command.5.4.5 DMA data transfer commands• RE

C141-E090-01EN 5 - 73Status readExpandedgfec, daCommandBSYINTRQDRDY~Parameter writeDRQData transfer• •• •DRQ[Multiword DMA transfer]• • • •DMACK-DMARQ

C141-E090-01EN5 - 745.5 Ultra DMA feature set5.5.1 OverviewUltra DMA is a data transfer protocol used with the READ DMA and WRITE DMAcommands. When t

C141-E090-01EN xiiiTABLESpage1.1 Specifications ...

C141-E090-01EN 5 - 755.5.2 Phases of operationAn Ultra DMA data transfer is accomplished through a series of Ultra DMA data in or data outbursts. Eac

C141-E090-01EN5 - 7611) The device shall drive the first word of the data transfer onto DD (15:0). This step mayoccur when the device first drives DD

C141-E090-01EN 5 - 773) The device shall stop generating DSTROBE edges within tRFS of the host negatingHDMARDY-.4) If the host negates HDMARDY- within

C141-E090-01EN5 - 7810) The device shall latch the host's CRC data from DD (15:0) on the negating edge ofDMACK-.11) The device shall compare the

C141-E090-01EN 5 - 7910) If the host has not placed the result of its CRC calculation on DD (15:0) since firstdriving DD (15:0) during (9), the host s

C141-E090-01EN5 - 809) The device shall assert DDMARDY- within tLI after the host has negated STOP. Afterasserting DMARQ and DDMARDY- the device shal

C141-E090-01EN 5 - 81b) Device pausing an Ultra DMA data out burst1) The device shall not pause an Ultra DMA burst until at least one data word of an

C141-E090-01EN5 - 829) The device shall compare the CRC data received from the host with the results of itsown CRC calculation. If a miscompare error

C141-E090-01EN 5 - 8311) The device shall compare the CRC data received from the host with the results of itsown CRC calculation. If a miscompare err

C141-E090-01EN5 - 84I) The CRC generator polynomial is : G (X) = X16 + X12 + X5 + 1.Note: Since no bit clock is available, the recommended approach

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C141-E090-01EN 5 - 855.6 Timing5.6.1 PIO data transferFigure 5.8 shows of the data transfer timing between the device and the host system.t6t12t11t10t

C141-E090-01EN5 - 865.6.2 Multiword data transferFigure 5.9 shows the multiword DMA data transfer timing between the device and the hostsystem.tFtEtHt

C141-E090-01EN 5 - 875.6.3 Ultra DMA data transferFigures 5.10 through 5.19 define the timings associated with all phases of Ultra DMA bursts.Table 5.

C141-E090-01EN5 - 885.6.3.2 Ultra DMA data burst timing requirementsTable 5.16 Ultra DMA data burst timing requirements (1 of 2)NAME MODE 0(in ns)MODE

C141-E090-01EN 5 - 89Table 5.16 Ultra DMA data burst timing requirements (2 of 2)NAME MODE 0(in ns)MODE 1(in ns)MODE 2(in ns)MODE 3(in ns)MODE 4(in ns

C141-E090-01EN5 - 905.6.3.3 Sustained Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:DD (15:0

C141-E090-01EN 5 - 915.6.3.4 Host pausing an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Notes:

C141-E090-01EN5 - 925.6.3.5 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.N

C141-E090-01EN 5 - 935.6.3.6 Host terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.No

C141-E090-01EN5 - 945.6.3.7 Initiating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:The

C141-E090-01EN 1 - 1CHAPTER 1 DEVICE OVERVIEW1.1 Features1.2 Device Specifications1.3 Power Requirements1.4 Environmental Specifications1.5 Acoustic

C141-E090-01EN 5 - 955.6.3.8 Sustained Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note:DD (15

C141-E090-01EN5 - 965.6.3.9 Device pausing an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.Note

C141-E090-01EN 5 - 975.6.3.10 Host terminating an Ultra DMA data out burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

C141-E090-01EN5 - 985.6.3.11 Device terminating an Ultra DMA data in burst5.6.3.2 contains the values for the timings for each of the Ultra DMA Modes.

C141-E090-01EN 5 - 995.6.4 Power-on and resetFigure 5.20 shows power-on and reset (hardware and software reset) timing.(1) Only master device is prese

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C141-E090-01EN 6 - 1CHAPTER 6 OPERATIONS6.1 Device Response to the Reset6.2 Address Translation6.3 Power Save6.4 Defect Management6.5 Read-Ahead Cach

C141-E090-01EN6 - 26.1.1 Response to power-onAfter the master device (device 0) releases its own power-on reset state, the master deviceshall check a

C141-E090-01EN 6 - 36.1.2 Response to hardware resetResponse to RESET- (hardware reset through the interface) is similar to the power-on reset.Upon re

C141-E090-01EN6 - 46.1.3 Response to software resetThe master device does not check the DASP- signal for a software reset. If a slave device ispresen

C141-E090-01EN1 - 2(4) Average positioning timeUse of a rotary voice coil motor in the head positioning mechanism greatly increases thepositioning spe

C141-E090-01EN 6 - 56.1.4 Response to diagnostic commandWhen the master device receives an EXECUTE DEVICE DIAGNOSTIC command and theslave device is pr

C141-E090-01EN6 - 66.2 Address TranslationWhen the IDD receives any command which involves access to the disk medium, the IDDalways implements the ad

C141-E090-01EN 6 - 76.2.2 Logical address(1) CHS modeLogical address assignment starts from physical cylinder (PC) 0, physical head (PH) 0, andphysica

C141-E090-02EN6 - 8(2) LBA modeLogical address assignment in the LBA mode starts from physical cylinder 0, physical head 0,and physical sector 1. The

C141-E090-02EN 6 - 9(1) Active modeIn this mode, all the electric circuit in the device are active or the device is under seek, read orwrite operation

C141-E090-01EN6 - 10• INITIALIZE DEVICE PARAMETERS command• CHECK POWER MODE command(4) Sleep modeThe power consumption of the drive is minimal in thi

C141-E090-01EN 6 - 116.4.1 Spare areaFollowing two types of spare area are provided in the user space.1) Spare sector for sector slip:used for alterna

C141-E090-01EN6 - 12(2) Alternate cylinder assignmentA defective sector is assigned to the spare sector in the alternate cylinder.This processing is p

C141-E090-01EN 6 - 136.5 Read-Ahead CacheAfter a read command which reads the data from the disk medium is completed, the read-ahead cache function re

C141-E090-01EN6 - 146.5.2 Caching operationThe caching operation is performed only at receipt of the following commands. The devicetransfers data fro

C141-E090-01EN 1 - 3(5) Error correction and retry by ECCIf a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes E

C141-E090-01EN 6 - 156.5.3 Usage of read segmentThis subsection explains the usage of the read segment buffer at following cases.(1) Miss-hit (no hit)

C141-E090-01EN6 - 16(3) Sequential readWhen the disk drive receives the read command that targets the sequential address to theprevious read command,

C141-E090-01EN 6 - 17b. Sequential hitWhen the last sector address of the previous read command is sequential to the lead sectoraddress of the receive

C141-E090-01EN6 - 18(3) Full hit (hit all)All requested data are stored in the data buffer. The disk drive starts transferring the requesteddata from

C141-E090-01EN 6 - 191) The disk drive sets the HAP to the address where the partially hit data is stored, and setsthe DAP to the address just after t

C141-E090-01EN6 - 206.6 Write CacheThe write cache function of the drive makes a high speed processing in the case that data to bewritten by a write c

C141-E090-01EN 6 - 21At the time that the drive has stopped the command execution after the error recovery hasfailed, the write cache function is disa

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C141-E090-01EN1 - 41.2 Device Specifications1.2.1 Specifications summaryTable 1.1 shows the specifications of the disk drive.Table 1.1 SpecificationsM

C141-E090-02EN iREVISION RECORDEdition Date published Revised contents01 Aug., 199902 Dec., 1999 • A dimension is added to the Figure 3.1.• “R” in t

C141-E090-01EN 1 - 51.2.2 Model and product numberTable 1.2 lists the model names and product numbers.Table 1.2 Model names and product numbersModel N

C141-E090-01EN1 - 6(3) Current Requirements and Power DissipationTable 1.3 lists the current and power dissipation.Table 1.3 Current and power dissipa

C141-E090-01EN 1 - 7(4) Current fluctuation (Typ.) when power is turned onFigure 1.1 Current fluctuation (Typ.) when power is turned on(5) Power on/of

C141-E090-01EN1 - 81.4 Environmental SpecificationsTable 1.4 lists the environmental specifications.Table 1.4 Environmental specificationsTemperature•

C141-E090-01EN 1 - 91.6 Shock and VibrationTable 1.6 lists the shock and vibration specification.Table 1.6 Shock and vibration specificationVibration

C141-E090-01EN1 - 10(4) Service lifeIn situations where management and handling are correct, the disk drive requires no overhaulfor five years when th

C141-E090-01EN 2 - 1CHAPTER 2 DEVICE CONFIGURATION2.1 Device Configuration2.2 System Configuration2.1 Device ConfigurationFigure 2.1 shows the disk d

C141-E090-01EN2 - 2(1) DiskThe outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disksused varies with the model, as d

C141-E090-01EN 2 - 32.2 System Configuration2.2.1 ATA interfaceFigures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pi

C141-E090-01EN2 - 4IMPORTANTHA (host adapter) consists of address decoder, driver, and receiver.ATA is an abbreviation of "AT attachment".

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C141-E090-01EN 3 - 1CHAPTER 3 INSTALLATION CONDITIONS3.1 Dimensions3.2 Mounting3.3 Cable Connections3.4 Jumper Settings3.1 DimensionsFigure 3.1 illus

C141-E090-02EN3 - 2Figure 3.1 Dimensions

C141-E090-01EN 3 - 33.2 Mounting(1) OrientationFigure 3.2 illustrates normal orientation for the disk drive. The disk drives can be mounted inany ori

C141-E090-01EN3 - 4Figure 3.3 Limitation of side-mountingFigure 3.4 Mounting frame structure5.0 or less4.5 orless2BFrame of systemcabinetDetails of BD

C141-E090-01EN 3 - 5(4) Ambient temperatureThe temperature conditions for a disk drive mounted in a cabinet refer to the ambienttemperature at a point

C141-E090-01EN3 - 6(5) Service areaFigure 3.6 shows how the drive must be accessed (service areas) during and after installation.Figure 3.6 Service ar

C141-E090-01EN 3 - 73.3 Cable Connections3.3.1 Device connectorThe disk drive has the connectors and terminals listed below for connecting external de

C141-E090-01EN3 - 83.3.2 Cable connector specificationsTable 3.2 lists the recommended specifications for the cable connectors for Host system thatdo

C141-E090-01EN 3 - 93.3.4 Power supply connector (CN1)Figure 3.9 shows the pin assignment of the power supply connector (CN1).(Viewed from cable side)

C141-E090-01EN3 - 10openConnector 2Connector 1System BoardConnectorPin 2 (Ground)Pin 19 (Ground)Pin 22 (Ground)Pin 24 (Ground)Pin 26 (Ground)Positio

C141-E090-01EN iiiPREFACEThis manual describes the MPE3xxxAH series, a 3.5-inch hard disk drive with a BUILT-IN controllerthat is compatible with the

C141-E090-01EN 3 - 11openHost detected CBLID- below VILHost Device 0Device 1with 80-conductor cablewith 40-conductor cablePDIAG-: CBLID- conductor PDI

C141-E090-01EN3 - 123.4 Jumper Settings3.4.1 Location of setting jumpersFigure 3.13 shows the location of the jumpers to select drive configuration an

C141-E090-01EN 3 - 133.4.2 Factory default settingFigure 3.14 shows the default setting position at the factory. (Master device setting)Figure 3.14 Fa

C141-E090-01EN3 - 14CSEL connected to the interface cable selectioncan be done by the special interface cable.864297531Figure 3.16 Jumper setting of C

C141-E090-01EN 3 - 15(3) Special jumper settings(a) 2.1 GB clip (Limit capacity to 2.1 GB)If the drive cannot be recognized by system with legacy BIOS

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C141-E090-01EN 4 - 1CHAPTER 4 THEORY OF DEVICE OPERATION4.1 Outline4.2 Subassemblies4.3 Circuit Configuration4.4 Power-on sequence4.5 Self-calibratio

C141-E090-01EN4 - 24.2.2 HeadFigure 4.1 shows the read/write head structures. The Numerals 0 to 7 indicate read/writeheads. These heads are raised f

C141-E090-01EN 4 - 34.2.5 Air filterThere are two types of air filters: a breather filter and a circulation filter.The breather filter makes an air i

C141-E090-01EN4 - 44.3 Circuit ConfigurationFigure 4.2 shows the disk drive circuit configuration.(1) Read/write circuitThe read/write circuit consist

iv C141-E090-01ENConventions for Alert MessagesThis manual uses the following conventions to show the alert messages. An alert message consists ofan

C141-E090-01EN 4 - 5Figure 4.2 MPE3xxxAH Block diagram

C141-E090-01EN4 - 64.4 Power-on SequenceFigure 4.3 describes the operation sequence of the disk drive at power-on. The outline isdescribed below.a) A

C141-E090-01EN 4 - 7c)b)a)Release heads fromactuator lockConfirming spindle motorspeedSelf-diagnosis 2• Data buffer write/read testThe spindle moto

C141-E090-01EN4 - 84.5 Self-calibrationThe disk drive occasionally performs self-calibration in order to sense and calibratemechanical external forces

C141-E090-01EN 4 - 94.5.2 Execution timing of self-calibrationSelf-calibration is executed when:• The power is turned on.• The self-calibration execut

C141-E090-01EN4 - 104.6 Read/write CircuitThe read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, theread circuit,

C141-E090-01EN 4 - 114.6.3 Read circuitThe head read signal from the PreAMP is regulated by the variable gain amplifier (VGA)circuit. Then the output

C141-E090-01EN4 - 124.6.4 Synthesizer circuitThe drive uses constant density recording to increase total capacity. This is different from theconventi

C141-E090-01EN 4 - 134.7.1 Servo control circuitFigure 4.4 is the block diagram of the servo control circuit. The following describes thefunctions of

C141-E090-01EN4 - 14c. Seek to specified cylinderDrives the VCM to position the head to the specified cylinder.d. CalibrationSenses and stores the the

C141-E090-01EN vLIABILITY EXCEPTION"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.Fujitsu is not lia

C141-E090-01EN 4 - 15(2) Servo burst capture circuitThe four servo signals can be synchronously detected by the STROB signal, full-waverectified integ

C141-E090-01EN4 - 164.7.2 Data-surface servo formatFigure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to(3

C141-E090-01EN 4 - 17POSCPADPOSDPOSBPOSA1.16 µs0.18 µs0.24 µs1.64 µsW/R Recovery Field0.84 µs0.84 µs0.84 µs0.92 µs0.48 µsPASSMASMSCD0.84 µsServoFrameD

C141-E090-01EN4 - 18(3) PreambleThis area is used to synchronize with the PLL, which is used to search the SSM by detectingthe ASM.(4) Gray code (incl

C141-E090-01EN 4 - 19(2) Seek operationUpon a data read/write request from the host, the MPU confirms the necessity of access to thedisk. If a read o

C141-E090-01EN4 - 20e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specificperiod, the MPU resets the SVC and starts fr

C141-E090-01EN 5 - 1CHAPTER 5 INTERFACE5.1 Physical Interface5.2 Logical Interface5.3 Host Commands5.4 Command Protocol5.5 Ultra DMA feature set5.6 T

C141-E090-01EN5 - 25.1 Physical Interface5.1.1 Interface signalsTable 5.1 shows the interface signals.Table 5.1 Interface signalsDescription Host Dir

C141-E090-01EN 5 - 35.1.2 Signal assignment on the connectorTable 5.2 shows the signal assignment on the interface connector.Table 5.2 Signal assignme

C141-E090-01EN5 - 4[signal] [I/O] [Description]DIOR– I DIOR– is the strobe signal asserted by the host to read deviceregisters or the data port.HDMARD

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C141-E090-01EN 5 - 5[signal] [I/O] [Description]IORDY O This signal is negated to extend the host transfer cycle of any hostregister access (Read or W

C141-E090-01EN5 - 65.2 Logical InterfaceThe device can operate for command execution in either address-specified mode; cylinder-head-sector (CHS) or

C141-E090-01EN 5 - 7Table 5.3 I/O registersI/O registersRead operation Write operationCommand block registers1 0 0 0 0 Data Data X'1F0'1 0 0

C141-E090-01EN5 - 85.2.2 Command block registers(1) Data register (X'1F0')The Data register is a 16-bit register for data block transfer bet

C141-E090-01EN 5 - 9[Diagnostic code]X'01': No Error Detected.X'02': HDC Register Compare ErrorX'03': Data Buffer Compar

C141-E090-01EN5 - 10(6) Cylinder Low register (X'1F4')The contents of this register indicates low-order 8 bits of the starting cylinder addr

C141-E090-01EN 5 - 11(9) Status register (X'1F7')The contents of this register indicate the status of the device. The contents of this regi

C141-E090-01EN5 - 12- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transferdata of word unit or byte unit between th

C141-E090-01EN 5 - 135.2.3 Control block registers(1) Alternate Status register (X'3F6')The Alternate Status register contains the same info

C141-E090-01EN5 - 145.3.1 Command code and parametersTable 5.4 lists the supported commands, command code and the registers that neededparameters are

C141-E090-01EN viiCONTENTSpageCHAPTER 1 DEVICE OVERVIEW ... 1 - 11.1 F

C141-E090-02EN 5 - 15Table 5.4 Command code and parameters (2 of 2)Command code (Bit) Parameters used7 6 5 4 3 2 1 0 FR SC SN CY DHSTANDBY IMMEDIATE 1

C141-E090-01EN5 - 165.3.2 Command descriptionsThe contents of the I/O registers to be necessary for issuing a command and the exampleindication of the

C141-E090-01EN 5 - 17Note:1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of theCH, CL and SN registers indicate

C141-E090-01EN5 - 18At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)1

C141-E090-01EN 5 - 19Figure 5.1 shows an example of the execution of the READ MULTIPLE command.• Block count specified by SET MULTIPLE MODE command =

C141-E090-01EN5 - 20(3) READ DMA (X'C8' or X'C9')This command operates similarly to the READ SECTOR(S) command except for followin

C141-E090-01EN 5 - 21At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)

C141-E090-01EN5 - 22At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)1

C141-E090-01EN 5 - 23At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)

C141-E090-01EN5 - 24The contents of the command block registers related to addresses after the transfer of a datablock containing an erred sector are

C141-E090-01ENviii3.4 Jumper Settings ... 3

C141-E090-01EN 5 - 251) Multiword DMA transfer mode 2:Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES co

C141-E090-01EN5 - 26At command completion (I/O registers contents to be read)1F7H(ST) Status information1F6H(DH)×L×DV End head No. /LBA [MSB]1F5H(CH)1

C141-E090-01EN 5 - 27(10) SEEK (X'7x', x : X'0' to X'F')This command performs a seek operation to the track and selects

C141-E090-01EN5 - 28(11) INITIALIZE DEVICE PARAMETERS (X'91')The host system can set the number of sectors per track and the maximum head nu

C141-E090-01EN 5 - 29At command issuance (I/O registers setting contents)1F7H(CM) 1 1 1 0 1 1 0 01F6H(DH)× × ×DV xx1F5H(CH)1F4H(CL)1F3H(SN)1F2H(SC)1F1

C141-E090-01EN5 - 30Table 5.5 Information to be read by IDENTIFY DEVICE command (1 of 4)Word Value Description0 X‘045A’ General Configuration *11 *2

C141-E090-01EN 5 - 31Table 5.5 Information to be read by IDENTIFY DEVICE command (2 of 4)*1 Word 0: General configurationBit 15: 0 = ATA device 0Bit

C141-E090-01EN5 - 32Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 4)*12 Word 63: Multiword DMA transfer modeBit 15-8: Currently u

C141-E090-01EN 5 - 33Table 5.5 Information to be read by IDENTIFY DEVICE command (4 of 4)*17 Word 85: Enable/disable Command set/feature enabledBit 1

C141-E090-01EN5 - 34(13) IDENTIFY DEVICE DMA (X'EE')When this command is not used to transfer data to the host in DMA mode, this commandfunc